FIG. 1 depicts a portion of a conventional magnetic random access memory (MRAM) 10. The conventional MRAM 10 includes conventional magnetic elements 12 and 14, conventional write line 16, conventional read and write word lines 18 and 20, respectively, data lines 22 and 24, write selection transistor 26 and read select transistors 28. The conventional magnetic elements 12 and 14, the write selection transistor 26, and read select transistors 28 can be considered to form a conventional magnetic storage cell. The conventional magnetic elements 12 and 14 that are configured to be in opposite high and low resistance states or vice versa. The conventional magnetic elements 12 and 14 are typically magnetic tunneling junctions (MTJs). Consequently, the conventional magnetic elements 12 and 14 have high and low resistance states, respectively, or vice versa.
The conventional MRAM 10 allows for differential reading of the conventional magnetic elements 12 and 14. During reading, the read select transistors 28 may be turned on to allow a read current to flow from the data lines 22 and 24 and through the conventional magnetic elements 12 and 14. Voltage (or current) signal carried by data lines 22 and 24 is fed into the input of a differential sensing amplifier (not shown). Only the difference of the signals are amplified and judged by a logic circuit to determine whether the cell is in a state of “0” or a state of “1”. Common mode noises are subtracted out using this differential sensing scheme. A large signal, the difference between maximum resistance and minimum resistances of the two MTJ bits in a cell, is available for sensing for both states. This type of conventional MRAM 10 offers high signal level and a high read speed. During writing, write selection transistor 26 is turned on, so that writing current is only applied to the cell being written. The conventional magnetic elements 12 and 14 in the MRAM 10 is written by turning write selection transistor 26 on, allowing current to flow through the write line 16. This current generates the magnetic field typically used to write to the conventional magnetic elements 12 and 14. Because the use of the write selection transistor 26, the write current is only applied to the cell being written. Consequently, issues due to half select writing cell disturb are reduced.
FIG. 2 depicts another conventional MRAM 10′. The conventional MRAM 10′ is analogous to the conventional MRAM 10, and thus has components that are labeled similarly. The conventional MRAM 10′ functions in a similar manner to the conventional MRAM 10. However, the write line 16′ around the magnetic elements 12′ and 14′, thereby approximately doubling the magnetic field at the magnetic elements 12′ and 14′. Because the magnetic field provided to the magnetic elements 12′ and 14′ is doubled, the write current may be reduced. The area consumed by a memory cells with a writing transistor is dominated by the size of the write selection transistor 26 or 26′. The size of the write selection transistor 26/26′ is determined by the write current through the write selection transistor 26/26′. Doubling the magnetic field from the same current allows a lower write current to be used. Consequently, a smaller write selection transistor 26/26′ can be used and the cell size reduced.
FIG. 3 depicts a conventional MRAM memory cell array 50 uses multiples of memory cells 52 in FIGS. 1 and 2. In FIG. 3, the read word lines 62 and write word line 54 run horizontally, while data lines 58 and 60 and write current line 56 run vertically. There are transistor switches at the ends of the lines (not shown) to connect them to power and ground sources. During a writing operation, write word line 54 is activated. Only those cells along the write word line 54 for which the write line 56 is also on are written. During a read operation, read word line 62 is activated. Only those cells along the read word line 62 having data lines 58 and 60 turned on are read. Note that other conventional architectures and other conventional cells exist. For example, some conventional MRAM may utilize reference MTJs in order to read the data stored in the cells. Other conventional MRAM may use magnetic fields produced by vertical bit lines and horizontal digit lines to switch the magnetic elements at their cross points. However, such conventional architectures may suffer from half select disturb problem for cells on the same bit line or digit line that are not intended to be switched.
A current trend in data storage is to increasing density and, therefore, smaller memory cell size. The cell size for the memory cells in the MRAM 10/10′ can be determined as follows. The variable f is the minimum feature size for lithography. The memory cells including the magnetic elements 12 and 14 and 12′ and 14′ shown in FIGS. 1 and 2 extend more than a length of 4 f in the horizontal and vertical directions. This is because there are two word lines 18/18′ and 20/20′, which utilize at least 4 f in width. There are also two data lines 22/22′ and 24/24′ that also utilize at least 4 f in width. Note that the minimum metal line width and spacing are typically wider than the minimum lithography width. Therefore, the estimate of 4 f offers a lower limit estimate of cell dimensions. Consequently, the cell size for the MRAMs 10/10′ may be at least 16 f2. However, such a small cell size would only allow a very small write selection transistor 26/26′ to fit within the cell and underneath the metal lines. If f is 180 nm, then the lateral dimension of the cell is 4 f or 720 nm. A conventional write selection transistor 26/26′ having a width of 720 nm would only supply a current of approximately 720 nm×0.0005 mA/nm or 0.36 mA. Such a write current may be one order of magnitude lower than the write current needed to provide a sufficient field for conventional MRAM memory cells. For a write selection transistor 26/26′ to control a write current of 6 mA (approximately one order of magnitude greater), a transistor width of 12,000 nm or 67 f is required. It may be possible to fold the gate poly line of the write selection transistor 26/26′ no more than three times to fit within the cell. This reduces the effective cell width by a factor of three to about 22 f. Therefore, the minimum cell size for the conventional MRAM 10/10′ may be 22 f×4 f=88 f2. In contrast, DRAM (12 f2), Flash (6 f2), and even some SRAM memories (40-100 f2) have significantly smaller cell sizes. In addition, other MRAM cells which use perpendicular bit and digit lines may have a cells size of about 40-50 f2 at f=180 nm, which is also much larger than DRAM and Flash.
Thus although the MRAMs 10/10′ is successful in solving some issues, it has a significantly larger cell size and a high cost. Consequently, this scheme may be unattractive for high density nonvolatile memory that is competitive with mainstream semiconductor memories such as SRAM, DRAM and Flash. In addition, other MRAM architectures may also have large cell sizes.
FIG. 4 depicts a graph 80 of the write current versus cell width. As the lithography critical dimension shrinks in the future, the switching field for conventional field switched MRAM, such as the conventional MRAM 10/10′ increases dramatically as the cell dimensions are reduced. This is due in part to increased demagnetizing effect in smaller magnetic elements. In addition, smaller magnetic elements have a lower thermal stability due to their shrinking volume. Consequently, smaller magnetic elements have a larger energy barrier to allow them to be thermally stable. For an MTJ, this is achieved by making the free layer thicker and harder to switch (requiring a higher write current). A higher write current translates into larger cell size, higher power consumption, and slower memory operation.
The phenomenon of spin transfer can be used as an alternative to or in addition to using an external switching field to switch the direction of magnetization of the free layer of a magnetic element, such as a conventional spin valve, MTJ, dual spin valve, dual MTJ, or other analogous structure. As can be seen in FIG. 4, the use of spin transfer is particularly attractive at lower cell dimensions and, therefore, lower write currents. To use the spin transfer effect to program a conventional MTJ to a first state, such as a logical “1”, current is driven through the magnetic element in a first direction. To use the spin transfer effect to program the magnetic element to a second state, such as a logical “0”, current is driven through the magnetic element in the opposite direction. To read the magnetic element a read current, which is less than the write current, is driven through the magnetic element. The output voltage or current can be compared to a reference voltage or current to determine whether a logical “0” or a logical “1” is stored in the magnetic storage cell.
Although magnetic elements utilizing spin transfer as a programming mechanism can be used in principle, one of ordinary skill in the art will readily recognize that there may be drawbacks. For example, the size of the magnetic storage cell may be large due to the currents driven through the magnetic element during a write operation. In addition, the write current driven through the selection transistor in opposite directions to program opposite states may be asymmetric. One of ordinary skill in the art will readily recognize that a current driven from the source to drain may be different from the current driven from the drain to the source for similar applied voltages. This asymmetry may be seen as follows. Assume that the magnetic element, for example an MTJ, is coupled with the drain of the transistor. The transistor drain current is given by the following equations under different conditions.
                                                                        I                D                            =                              μ                ⁢                                                                  ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  (                                                            V                      GS                                        -                                          V                      T                                                        )                                ⁢                                  V                  DS                                                      ,                                                  ⁢            for                                    ⁢                  V          DS                ⁢                                        <<                          (                                                V                  GS                                -                                  V                  T                                            )                                                          Eq        .                                  ⁢                  (          1          )                                                              I            D                    =                      μ            ⁢                                                  ⁢                          C              ox                        ⁢                                          W                L                            ⁡                              [                                                                            (                                                                        V                          GS                                                -                                                  V                          T                                                                    )                                        ⁢                                          V                      DS                                                        -                                                            V                      DS                      2                                        2                                                  ]                                                    ,                                  ⁢                              for            ⁢                                                  ⁢                          V              DS                                <                                    V              GS                        -                          V              T                                                          Eq        .                                  ⁢                  (          2          )                                                              I                          D              ,              sat                                =                      μ            ⁢                                                  ⁢                          C              ox                        ⁢                          W              L                        ⁢                                                            (                                                            V                      GS                                        -                                          V                      T                                                        )                                2                            2                                      ,                                  ⁢                              for            ⁢                                                  ⁢                          V              DS                                >                                    V              GS                        -                          V              T                                                          Eq        .                                  ⁢                  (          3          )                    
Eq. (1) applied for a transistor under MTJ element reading condition, where the bias voltage and current through the MTJ and transistor is lower. The maximum value ID of Eq. (2) equals the value Of, ID,sat in Eq. (3). This is the current desired during a writing operation to provide substantially a maximum current possible through a minimum sized transistor. Such a situation may allow for a smaller transistor, smaller magnetic storage cell sizes and, therefore, a higher density spin transfer based memory. There is a limit to how large a VGS can be applied in order to ensure that a maximum electric field for the transistor is not exceeded and transistor gate oxide reliability problems are avoided. For a 90 nm node, the gate voltage is usually less than 1.2 volts. If VT is made to be 0.2 volts, then VDS beyond 1.0 volt saturates the ID value. When VDS is significantly greater VGS, hot electron reliability problems may occur. Using this information, it is possible to calculate the writing current that can be provided by a particular transistor. Such a calculation indicates that not only are the writing currents are asymmetric for writing the two states, but also there is a large loss in switching current in at least one writing case.
Accordingly, what is needed is a magnetic memory that may be suitable for higher densities and preferably utilizing a localized phenomenon for writing, such as spin transfer. The present invention addresses such a need.